Instruction Set

Type 0:	Arithmetic / Logic / Shift	3 Register
	add	Rp, Rm, Rn	Rp <- Rm +    Rn
	sub	Rp, Rm, Rn	Rp <- Rm -    Rn
	and	Rp, Rm, Rn	Rp <- Rm and  Rn
	nand	Rp, Rm, Rn	Rp <- Rm nand Rn
	or	Rp, Rm, Rn	Rp <- Rm or   Rn
	eor	Rp, Rm, Rn	Rp <- Rm eor  Rn
	asl	Rp, Rm, Rn	Rp <- Rm <<   Rn
	asr	Rp, Rm, Rn	Rp <- Rm >>   Rn


Type 1: Arithmetic / Logic / Shift	Immediate
	addi	Rp, Rm, #d	Rp <- Rm +    d
	subi	Rp, Rm, #d	Rp <- Rm -    d
	andi	Rp, Rm, #d	Rp <- Rm and  d
	nandi	Rp, Rm, #d	Rp <- Rm nand d
	ori	Rp, Rm, #d	Rp <- Rm or   d
	eori	Rp, Rm, #d	Rp <- Rm eor  d
	asli	Rp, Rm, #d	Rp <- Rm <<   d
	asri	Rp, Rm, #d	Rp <- Rm >>   d

Type 2: Conditional Branch
	beq	Rp, #d		PC <- PC + d	if Rp == 0
	bne	Rp, #d		PC <- PC + d	if Rp != 0
	blt	Rp, #d		PC <- PC + d	if Rp <  0
	ble	Rp, #d		PC <- PC + d	if Rp <= 0
	bgt	Rp, #d		PC <- PC + d	if Rp >  0
	bge	Rp, #d		PC <- PC + d	if Rp >= 0

Type 3: Branch to Subroutine
	bsr	#d		data[-(sp)] 	<- SP
				PC		<- PC + d
Type 4: Jump
	jmp	#d		PC		<- PC + d

Type 5: Memory Access
	ldd	Rp, #d		Rp 		<- data[R7 + d]
	lda	Rp, #d		Rp		<- R7 + d
	sw	Rp, #d		data[R7 + d]	<- Rp
	sb	Rp, #d		data[R7 + d]	<- Rp	(lsb)

Type 6a:
	lsp	#d		SP 		<- d << 8
	lbr	#d		BR 		<- d << 8
	swi	#d		-(SSP)		<- PC
				-(SSP)		<- SR
				SR		<- SR & ~SR_USER
				PC		<- d

Type 6b:
	gsp	Rp		Rp <- SP
	ssp	Rp		SP <- Rp

Type 6c:
These instructions will generate a SR_PRIV fault if executed
whilst in user mode.

	gsr	Rp		Rp <- SR
	ssr	Rp		Rp <- SP
	gusp	Rp		Rp <- USP

Type 6d: 
	psh	Rp		-(SP)	<- Rp
	pop	Rp		Rp	<- (SP)+

Type 7:
	rti			SR <- (SSP)+
				PC <- (SSP)+
				
	rts			PC <- (SP)+

	nop			nothing

	stop			SR <- SR != SR_STOP